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| MC100LVE222 3.3 V ECL 1:15 Differential /1//2 Clock Driver The MC100LVE222 is a low skew 1:15 differential /1//2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single-ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. The LVE222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs. The device tpd is affected by the quantity of output pairs terminated with a minimum occurring with only one output pair and increasing about 10-20 ps for all output pairs. Relative skew distribution is not affected as more pairs are terminated, but the increased tpd does shift the entire distribution. Unused output pairs should be left unterminated (open) to reduce power and switching noise. The MC100LVE222, as with most ECL devices, can be operated from a positive VCC supply in PECL mode. This allows the LVE222 to be used for high performance clock distribution in +3.3 V systems. Designers can take advantage of the LVE222's performance to distribute low skew clocks across the backplane or the board. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. All power supply pins must be connected. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, refer to Application Note AN1560/D. http://onsemi.com MARKING DIAGRAM* 52 1 MC100LVE 222 TQFP FA SUFFIX CASE 848D A WL YY WW AWLYYWW = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device MC100LVE222FA MC100LVE222FAR2 Package TQFP TQFP Shipping 160 Units/Tray 1500 Tape & Reel * * * * * * * * * * * * 200 ps Part-to-Part Skew 50 ps Output-to-Output Skew Selectable 1x or 1/2x Frequency Outputs ESD Protection: >2 kV HBM, >200 V MM The 100 Series Contains Temperature Compensation PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V Internal Input Pulldown Resistors Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test Moisture Sensitivity Level 2 For Additional Information, refer to Application Note AND8003/D Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 684 devices (c) Semiconductor Components Industries, LLC, 2001 1 April, 2001- Rev. 4 Publication Order Number: MC100LVE222/D MC100LVE222 VCCO VCCO VCCO Qc0 Qc0 Qc1 Qc1 Qc2 Qc2 Qc3 Qc3 NC NC FUNCTION TABLE Function VCCO Qb2 Qb2 Qb1 Qb1 Qb0 Qb0 VCCO Qa1 Qa1 Qa0 Qa0 VCCO 40 41 42 43 44 45 46 47 48 49 50 51 52 39 38 37 36 35 34 33 32 31 30 29 28 27 Input 26 25 24 23 22 21 Qd0 Qd0 Qd1 Qd1 Qd2 Qd2 Qd3 Qd3 Qd4 Qd4 Qd5 Qd5 VCCO MR CLK_Sel fseln L Active CLK0 /1 H Reset CLK1 /2 PIN DESCRIPTION PIN CLK0, CLK0 CLK1, CLK1 CLK_Sel MR Qa0:1, Qa0:1 Qb0:2, Qb0:2 Qc0:3, Qc0:3 Qd0:5, Qd0:5 fseln VBB VCC, VCCO VEE NC FUNCTION ECL Differential Input Clock ECL Differential Input Clock ECL Clock Select ECL Master Reset ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL 1 or 2 Select Reference Voltage Output Positive Supply Negative Supply No Connect 52-Lead TQFP (Top View) 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK_Sel VBB fsela fselb CLK0 CLK0 CLK1 CLK1 Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Pinout Assignment MR CLK0 CLK0 CLK1 CLK1 CLK_Sel VBB fsela 3 fselb 4 fselc 6 fseld Qd0:5 Qd0:5 Qc0:3 Qc0:3 Qb0:2 Qb0:2 /1 /2 2 Qa0:1 Qa0:1 Figure 2. Logic Diagram http://onsemi.com 2 fseld VCC fselc VEE MR MC100LVE222 CLK RESET Q 1/2Q Figure 3. Timing Diagram MAXIMUM RATINGS (Note 1.) Symbol VCC VEE VI Iout IBB TA Tstg JA JC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode Input Voltage C ode u o age NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Wave Solder 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 52 TQFP 52 TQFP 52 TQFP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 8 to 0 -8 to 0 6 to 0 o -6 to 0 50 100 0.5 -40 to +85 -65 to +150 70 48 TBD 265 Units V V V V mA mA mA C C C/W C/W C/W C 1. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 3 MC100LVE222 LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 2.) -40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 3.) Output LOW Voltage (Note 3.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 7.) Vpp < 500 mV Vpp y 500 mV Input HIGH Current Input LOW Current Others CLK0, CLK1 0.5 -300 2215 1470 2135 1490 1.92 Min Typ 122 2295 1605 Max 136 2420 1745 2420 1825 2.04 2275 1490 2135 1490 1.92 Min 25C Typ 122 2345 1595 Max 136 2420 1680 2420 1825 2.04 2275 1490 2135 1490 1.92 Min 85C Typ 125 2345 1595 Max 139 2420 1680 2420 1825 2.04 Unit mA mV mV mV mV V 1.3 1.6 2.9 2.9 150 1.2 1.5 2.9 2.9 150 1.2 1.5 2.9 2.9 150 V V A A A IIH IIL 0.5 -300 0.5 -300 NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 3. Outputs are terminated through a 50 ohm resistor to VCC -2 V. 4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min). LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = -3.3 V (Note 5.) -40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 6.) Output LOW Voltage (Note 6.) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Output Voltage Reference Input HIGH Voltage Common Mode Range (Differential) (Note 7.) Vpp < 500 mV Vpp y 500 mV Input HIGH Current Input LOW Current Others CLK0, CLK1 0.5 -300 -1085 -1830 -1165 -1810 -1.38 Min Typ 122 -1005 -1695 Max 136 -880 -1555 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 25C Typ 122 -955 -1705 Max 136 -880 -1620 -880 -1475 -1.26 -1025 -1810 -1165 -1810 -1.38 Min 85C Typ 125 -955 -1705 Max 139 -880 -1620 -880 -1475 -1.26 Unit mA mV mV mV mV V -2.0 -1.7 -0.4 -0.4 150 -2.1 -1.8 -0.4 -0.4 150 -2.1 -1.8 -0.4 -0.4 150 V V A A A IIH IIL 0.5 -300 0.5 -300 NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 5. Input and output parameters vary 1:1 with VCC. VEE can vary 0.3 V. 6. Outputs are terminated through a 50 ohm resistor to VCC -2 volts. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. VIHCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The VIL level must be such that the peak to peak voltage is less than 1.0 V and greater than or equal to VPP(min). http://onsemi.com 4 MC100LVE222 AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -3.3 V (Note 8.) -40C Symbol fmax tPLH tPHL Characteristic Maximum Toggle Frequency Propagation Delay to Output IN (differential) (Note 9.) IN (single-ended) (Note 10.) MR Within-Device Skew (Note 11.) Part-to-Part Skew (Differential) Cycle-to-Cycle Jitter Input Swing (Differential) (Note 12.) Output Rise/Fall Time 20%-80% 400 200 TBD 1000 600 400 200 1040 990 1100 Min Typ TBD Max Min 25C Typ TBD 1240 1290 1400 50 200 TBD 1000 600 400 200 1080 1030 1170 1180 1180 1320 1280 1330 1470 50 200 TBD 1000 600 1120 1070 1220 Max Min 70C Typ TBD 1220 1220 1370 1320 1370 1520 50 200 ps ps mV ps Max Unit GHz ps 1140 1140 1250 tskew tJITTER VPP tr/tf 8. VEE can vary 0.3 V. 9. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 10. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 11. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device. 12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the LVE222. A differential input as low as 50 mV will still produce full ECL levels at the output. Q Driver Device Qb 50 W 50 W D Receiver Device Db V TT V TT = V CC - 2.0 V Figure 4. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices) Resource Reference of Application Notes AN1404 AN1405 AN1406 AN1503 AN1504 AN1560 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020 - - - - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) ECLinPS I/O SPICE Modeling Kit Metastability and the ECLinPS Family Low Voltage ECLinPS SPICE Modeling Kit Interfacing Between LVDS and ECL ECLinPS Lite Translator ELT Family SPICE I/O Model Kit Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes Termination of ECL Logic Devices http://onsemi.com 5 MC100LVE222 PACKAGE DIMENSIONS FA SUFFIX TQFP PACKAGE CASE 848D-03 ISSUE D 4X -X- X=L, M, N 4X TIPS 0.20 (0.008) H L-M N 0.20 (0.008) T L-M N C L AB G 52 1 40 39 AB VIEW Y -M- B V PLATING 3X VIEW Y -L- F BASE METAL B1 13 14 26 27 J V1 0.13 (0.005) A1 S1 A S -N- SECTION AB-AB ROTATED 90_ CLOCKWISE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H . 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --0_ 12 _ REF 5_ 13 _ C -H- -T- SEATING PLANE 4X 2 0.10 (0.004) T 4X 3 VIEW AA 0.05 (0.002) S W 1 C2 2 X R R1 0.25 (0.010) GAGE PLANE K C1 E Z VIEW AA DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3 http://onsemi.com 6 EEEE CCCC EEEE CCCC EEEE M U D T L-M S N S MC100LVE222 Notes http://onsemi.com 7 MC100LVE222 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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